US 2026/0020286 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.

Claims20

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming a first active pattern including first semiconductor layers and first sacrificial layers alternately stacked on a peripheral region of a substrate;
forming a second active pattern including second semiconductor layers and second sacrificial layers alternately stacked on a logic cell region of the substrate;
forming first source/drain patterns on the first active pattern;
forming second source/drain patterns on the second active pattern;
selectively removing the first sacrificial layers and forming a first gate electrode;
selectively removing the second sacrificial layers and forming a second gate electrode;
forming a gate capping pattern on the first gate electrode and the second gate electrode;
forming a first mask layer on the logic cell region;
forming a contact hole penetrating the gate capping pattern and exposing the first gate electrode;
and
forming a dielectric layer in the contact hole.

8 more elements

A method of manufacturing a semiconductor device, comprising:

forming a first active pattern including first semiconductor layers and first sacrificial layers alternately stacked on a peripheral region of a substrate;
forming a second active pattern including second semiconductor layers and second sacrificial layers alternately stacked on a peripheral region of the substrate, spaced apart from the first active pattern in a first direction;
forming a third active pattern including third semiconductor layers and third sacrificial layers alternately stacked on the logic cell region;
forming a fourth active pattern including fourth semiconductor layers and fourth sacrificial layers alternately stacked on the logic cell region, spaced apart from the third active pattern in the first direction;
selectively removing the first sacrificial layers and the second sacrificial layers to expose first empty spaces;
selectively removing the third sacrificial layers and the fourth sacrificial layers to expose second empty spaces;
forming a first gate electrode in the first empty spaces;
forming a second gate electrode in the second empty spaces;
forming a gate capping pattern on the first gate electrode and the second gate electrode;
forming a first mask layer on the logic cell region;
forming a contact hole penetrating the gate capping pattern and exposing the first gate electrode;
forming a dielectric layer in the contact hole;
and
forming a first gate contact filling the contact hole on the dielectric layer.

11 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims20