Stacked gate-all-around finfet and method forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
Life of this patent
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Abstract
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
Claims21
(canceled)
A device comprising:
- a bulk semiconductor substrate;
- a semiconductor strip over the bulk semiconductor substrate, wherein the semiconductor strip comprises a first edge and a second edge, and wherein the first edge and the second edge are opposing edges of the semiconductor strip;
- shallow trench isolation regions on opposite sides of the semiconductor strip;
- a plurality of semiconductor layers spaced apart from each other and overlapping the semiconductor strip, wherein upper ones of the plurality of semiconductor layers overlap respective lower ones of the plurality of semiconductor layers, and wherein a semiconductor layer of the plurality of semiconductor layers comprises:
- a third edge vertically aligned to the first edge;
- and
- a fourth edge vertically aligned to the second edge;
- a gate stack encircling the plurality of semiconductor layers, wherein the gate stack comprises:
- a gate dielectric;
- and
- a gate electrode encircling the gate dielectric;
- and
- source/drain regions connected to opposite ends of the plurality of semiconductor layers.
A device comprising:
- a bulk semiconductor substrate;
- a semiconductor strip over the bulk semiconductor substrate;
- a first dielectric layer over and contacting the semiconductor strip;
- shallow trench isolation regions contacting opposite sidewalls of the semiconductor strip;
- a second dielectric layer over and contacting the first dielectric layer and the shallow trench isolation regions;
- a source region and a drain region;
- a semiconductor layer connecting the source region to the drain region, wherein the semiconductor layer overlaps the semiconductor strip;
- a gate dielectric on the semiconductor layer;
- and
- a gate electrode contacting both of the second dielectric layer and the gate dielectric.
A device comprising:
- a first shallow trench isolation region;
- a second shallow trench isolation region spaced apart from the first shallow trench isolation region;
- a semiconductor strip between the first shallow trench isolation region and the second shallow trench isolation region;
- a first dielectric layer overlapping the semiconductor strip;
- a semiconductor layer overlapping a center the first dielectric layer;
- and
- a gate stack comprising a gate dielectric and a gate electrode on the gate dielectric, wherein the gate stack encircles the semiconductor layer.
Dependencies are inferred from the claim text.