Crossbar circuits utilizing ovonic threshold switching (ots) memory devices

#The implementations of the disclosure relate generally to electronic devices and, more specifically, to crossbar circuits utilizing ovonic threshold switching (OTS) memory devices.

#A crossbar circuit may refer to a circuit structure with interconnecting electrically conductive lines sandwiching a memory element, such as a resistive switching material, at their intersections. The resistive switching material may include, for example, a memristor (also referred to as resistive random-access memory (RRAM or ReRAM)). Crossbar circuits may be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc.

#The following is a simplified summary of the disclosure to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is intended to neither identify key or critical elements of the disclosure, nor delineate any scope of the particular implementations of the disclosure or any scope of the claims. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

#The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding.

#FIG. 1 is a schematic diagram illustrating an example of a crossbar circuit in accordance with some embodiments of the present disclosure.

#FIGS. 2A and 2B depict I-V characteristics of an example OTS memory device in accordance with some embodiments of the present disclosure.

#Aspects of the disclosure provide memory devices utilizing Ovonic threshold switching (OTS) materials and crossbar circuits of the memory devices. OTS switching refers to a phenomenon where a material transitions from an insulating state to a conductive state when a specific threshold voltage is applied. Materials that exhibit OTS switching characteristics include chalcogenides, which are compounds containing at least one chalcogen element (such as sulfur (S), selenium (Se), tellurium (Te), etc.) combined with more electropositive elements, such as SiGeAsSe, GeSe, GeSbTe, and AgInSbTe. OTS is an electron-dominated switching process, which requires minimal ionic defects in the amorphous material. OTS chalcogenides may need to maintain amorphous states to ensure a very low leakage current.

#OTS devices have traditionally been used as switches or selectors utilizing their high on/off current ratio. For example, when a voltage exceeding the threshold voltage (VTH) is applied, the device changes from a low conductance (Off) state to a high conductance state (On) state. When the applied voltage is removed, the device returns to the low conductance (Off) state. The OTS switching is volatile. An OTS device may be used as a selector in a 1S1R configuration in a crossbar array, with S as the selector for the volatile switching, and R as the memristor for the non-volatile switching.

#According to one or more aspects of the present disclosure, an OTS memory device may be used as a selector and a memory device in a similar 1S1R configuration in a crossbar array, with the new S performing as a selector and a memristor. The OTS memory device is a selector as well as a memristor, using the migration effect of ionic defects in the chalcogenide under switching polarities to store information (referred to as the OTS-memory effect). This effect may be enhanced by the interface layers applied in the OTS memory devices as described herein. The ability of OTS memory devices to function as both selectors and memristors allows for a more compact 1-memristor (1R) design in crossbar arrays. This may eliminate the need for a separate selector element, leading to higher memory density and lower fabrication and operation costs.