Semiconductor package having stacked interconnected semiconductor chips

A method of manufacturing a semiconductor package, the method comprising:

• preparing a first semiconductor chip;
• the first semiconductor chip including a first substrate and a first wiring layer on an active surface of the first substrate;
• preparing second semiconductor chips, each of the second semiconductor chips including a second substrate, a second wiring layer on an active surface of the second substrate, and front connection pads on the second wiring layer;
• attaching an insulating adhesive layer covering the second wiring layer of each of the second semiconductor chips;
• and
• sequentially stacking the second semiconductor chips on the first semiconductor chip such that the insulating adhesive layer is attached to an inactive surface of the first substrate or to an inactive surface of the second substrate of each of the second semiconductor chips,
• wherein rear connection pads are attached to the inactive surface of the first substrate of the first semiconductor chip or to the inactive surface of the second substrate of each of the second semiconductor chips,
• wherein for each insulating adhesive layer, the sequentially stacking second semiconductor chips on the first semiconductor chip includes forming support structures and chip connection terminals each penetrating the insulating adhesive layer,
• wherein each of the support structures includes a first support post attached to the second wiring layer and a second support post attached to the inactive surface the first substrate or to the inactive surface of the second substrate of a corresponding one of the second semiconductor chips,
• wherein for each of the rear connection pads and corresponding front connection pads, the front connection pads face the rear connection pads, and the chip connection terminals are attached to the front connection pads and the rear connection pads, and
• wherein each of the support structures is spaced apart from the front connection pads, the rear connection pads, and the chip connection terminals, has a vertical height greater than a vertical height of each of the chip connection terminals, and includes a metal.

A method of manufacturing a semiconductor package, the method comprising:

• preparing a buffer chip;
• the buffer chip including a first substrate and a first wiring layer on an active surface of the first substrate;
• preparing memory cell chips, each of the memory cell chips including a second substrate, a second wiring layer on an active surface of the second substrate, and front connection pads on the second wiring layer;
• attaching an insulating adhesive layer covering the second wiring layer of each of the memory cell chips;
• and
• sequentially stacking the memory cell chips on the buffer chip such that the insulating adhesive layer is attached to an inactive surface of the first substrate or to an inactive surface of the second substrate of each of the memory cell chips,
• wherein rear connection pads are attached to the inactive surface of the first substrate of the buffer chip or to the inactive surface of the second substrate of each of the memory cell chips,
• wherein for each insulating adhesive layer, the sequentially stacking memory cell chips on the buffer chip includes forming support structures and chip connection terminals each penetrating the insulating adhesive layer,
• wherein each of the support structures includes a first support post attached to the second wiring layer and a second support post attached to the inactive surface the first substrate or to the inactive surface of the second substrate of a corresponding one of the memory cell chips,
• wherein for each of the rear connection pads and corresponding front connection pads, the front connection pads face the rear connection pads, and the chip connection terminals are attached to the front connection pads and the rear connection pads,
• wherein the support structures are electrically isolated from active circuitry in the buffer chip and the memory cell chips, and
• wherein a lower surface of the first support post of each of the support structures contacts an upper surface of the second support post of a corresponding one of the support structures.