Semiconductor package

A semiconductor package comprising:

• a package substrate comprising a first upper connection pad and a second upper connection pad, the first upper connection pad and the second upper connection pad being on a top surface of the package substrate;
• a first stacked chip assembly comprising a plurality of first semiconductor chips stacked in a step-like shape on the package substrate, a first chip pad on a top surface of each of the plurality of first semiconductor chips, and a first conductive pattern, the first chip pad being adjacent to a first chip edge of each of the plurality of first semiconductor chips;
• a second stacked chip assembly comprising a plurality of second semiconductor chips stacked in a step-like shape on the first stacked chip assembly, a second chip pad on a top surface of each of the plurality of second semiconductor chips, and a second conductive pattern, the second chip pad being adjacent to a second chip edge of each of the plurality of second semiconductor chips;
• and
• a first encapsulation member surrounding the first stacked chip assembly;
• wherein the first conductive pattern is along top surfaces and side surfaces of the plurality of first semiconductor chips, and the first conductive pattern is connected with at least one of a plurality of first chip pads and the first upper connection pad,
• wherein the second conductive pattern is along the top surfaces and the side surfaces of the plurality of first semiconductor chips and a surface of the first encapsulation member, and the second conductive pattern is connected with at least one of a plurality of second chip pads and the second upper connection pad, and
• wherein a first cover insulation layer is on the top surface of the package substrate, the first cover insulation layer covering the first conductive pattern on the top surface of the package substrate.

A semiconductor package comprising:

• a package substrate comprising a plurality of upper connection pads on a top surface of the package substrate;
• a plurality of semiconductor chip stacks, each semiconductor chip stack stacked in a step-like shape in one direction, wherein the plurality of semiconductor chip stacks are sequentially stacked in an overall zigzag shape, and two adjacent semiconductor chip stacks are stacked in different step-wise directions;
• a plurality of encapsulation members on the package substrate, each encapsulation member surrounding a corresponding semiconductor chip stack among the plurality of semiconductor chip stacks;
• and
• a plurality of conductive patterns configured to interconnect the plurality of semiconductor chip stacks and corresponding upper connection pads,
• wherein the plurality of semiconductor chip stacks comprise a first semiconductor chip stack and a second semiconductor chip stack on the first semiconductor chip stack, the first semiconductor chip stack being closest to the package substrate among the plurality of semiconductor chip stacks,
• wherein on the first semiconductor chip stack, the conductive pattern extends along a surface of the semiconductor chip and the top surface of the package substrate,
• wherein on the second semiconductor chip stack, conductive patterns extend along the surface of the semiconductor chip, a surface of one of the plurality of encapsulation members, and the top surface of the package substrate, respectively,
• wherein a separating insulation layer is between side surfaces of the plurality of semiconductor chips included in the plurality of semiconductor chip stacks and a plurality of corresponding conductive patterns,
• wherein the plurality of encapsulation members comprise a first encapsulation member and a second encapsulation member,
• wherein the first encapsulation member surrounds the first semiconductor chip stack, and the second encapsulation member surrounds the first semiconductor chip stack and the first encapsulation member, and
• wherein a plurality of cover insulation layers respectively cover the plurality of conductive patterns and extend on the top surface of the package substrate in semiconductor chip stacks other than an uppermost semiconductor chip stack among the plurality of semiconductor chip stacks.