Semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorJunbyeong LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes: a semiconductor chip; a package substrate below the semiconductor chip in a vertical direction; and a plurality of connection pads on a lower surface of the package substrate, wherein the plurality of connection pads include: a first group of connection pads having a first width, and a second group of connection pads having a second width smaller than the first width, and wherein the first group of connection pads are provided closer to an edge boundary of a contact surface between the semiconductor chip and the package substrate than the second group of connection pads.
Claims20
A semiconductor package comprising:
- a plurality of semiconductor chips stacked vertically, and comprising a first semiconductor chip at a bottom in a vertical direction;
- a package substrate below the plurality of semiconductor chips, and comprising:
- a contact boundary defined by the first semiconductor chip, and
- a first region that is a ring-shaped region extending along the contact boundary with a predetermined width,
- a second region inside the first region,
- and a third region outside the first region;
- a plurality of connection pads on a lower surface of the package substrate;
- and
- a plurality of connection bumps below the plurality of connection pads, respectively,
- wherein the plurality of connection pads comprise:
- a first group of connection pads at least a portion of each of which is within the first region, and
- a second group of connection pads within the second region and the third region, and
- wherein a first width of the first group of connection pads is greater than a second width of the second group of connection pads.
A semiconductor package comprising:
- a semiconductor chip;
- a package substrate below the semiconductor chip in a vertical direction;
- and
- a plurality of connection pads on a lower surface of the package substrate,
- wherein the plurality of connection pads comprise:
- a first group of connection pads having a first width, and
- a second group of connection pads having a second width smaller than the first width, and
- wherein the first group of connection pads are closer to an edge boundary of a contact surface between the semiconductor chip and the package substrate than the second group of connection pads.
A semiconductor package comprising:
- a package substrate;
- a semiconductor chip on the package substrate, in a vertical direction;
- a plurality of connection pads on a lower surface of the package substrate, in the vertical direction;
- a plurality of connection bumps below the plurality of connection pads, respectively;
- and
- a protective layer covering at least portions of the plurality of connection pads and surrounding at least portions of the plurality of connection bumps,
- wherein the plurality of connection pads comprise:
- a first connection pad adjacent to an edge boundary of a contact surface between the semiconductor chip and the package substrate, and
- a second connection pad around the first connection pad, and
- wherein a first contact area between the first connection pad and the protective layer is larger than a second contact area between the second connection pad and the protective layer.
Dependencies are inferred from the claim text.