Method for manufacturing via

A method for manufacturing a via, comprising:

• providing an underlying structure, and forming a first dielectric layer on a surface of the underlying structure;
• performing patterned etching on the first dielectric layer to form a via opening;
• forming a first metal layer that fully fills the via opening and extends to a top surface of the first dielectric layer outside the via opening;
• performing first-time metal chemical mechanical polishing (CMP), wherein the first-time metal CMP removes the first metal layer on the top surface of the first dielectric layer outside the via opening, and a top surface of the first metal layer in the via opening is located below the top surface of the first dielectric layer;
• performing second-time dielectric etch back, wherein the second-time dielectric etch back selectively etches the first dielectric layer and lowers the top surface of the first dielectric layer as being below the top surface of the first metal layer, the via is composed of the first metal layer filling the via opening and comprises a metal protrusion formed by the first metal layer above the top surface of the first dielectric layer, the second-time dielectric etch back ensures that the metal protrusion is uniform in a plane and is free of scratch defects;
• and
• forming a pattern of an upper metal interconnection layer, wherein the metal protrusion ensures that the via is in full contact with the pattern of the upper metal interconnection layer and avoids a high resistance and an open circuit.