Network-driven, inbound network data orchestration
AssigneesUniversity of Kansas, The Board of Trustees of the University of Illinois
InventorsMohammad Alian, Nam Sung Kim, Siddharth Agarwal
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AssigneesUniversity of Kansas, The Board of Trustees of the University of Illinois
InventorsMohammad Alian, Nam Sung Kim, Siddharth Agarwal
Estimating the term…
Aspects provide an intelligent direct input/output (IDIO) architecture for facilitating movement of data between processor cores and memories. A data packet is received at a network interface and classified based on its association with an application being processed by one or more cores of a processor. The disclosed IDIO architecture may determine to steer the data packet to a cache memory (e.g., a last level cache (LLC) or middle level cache (MLC)) or random access memory in response to receiving the data packet. The determination to steer the data packet to a particular memory may be based on characteristics of the data packet, the application, or other metrics. Where the data packet is steered to the MLC, the data packet may first be steered to the LLC and then prefetched to the MLC. The application may provide control information to invalidate a cacheline associated with the data packet one used.
A method comprising:
A method comprising:
A system comprising:
A system comprising:
Dependencies are inferred from the claim text.