Enhanced integer encoding for arithmetic processors

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit including:
• a processing element (PE) array including a plurality of rows of PEs and a plurality of columns of PEs, wherein each of the PEs includes an arithmetic circuit configured to mathematically combine activation operands and weight operands;
• a weight memory configured to supply weight operands to PEs in the PE array;
• an activation memory configured to supply activation operands to PEs in the PE array;
• and
• an encoder coupled to the activation memory and to the PE array, wherein the encoder includes a multiplexing circuit configured to encode a signed N-bit activation operand as a signed N-M bit higher order portion representing an integer value [signed {aN-1 . . . aN-M}+aN-1]*2M and a signed M+1 bit lower order portion representing an integer value signed {aNaN-M-1 . . . a0}.

A method of processing in a processing unit including a plurality of processing elements (PEs) arranged in a PE array, the method comprising:

• storing, in a weight memory, weight operands for PEs in the PE array;
• storing in an activation memory, activation operands for PEs in the PE array;
• encoding the activation operands by an encoder coupled to the activation memory and to the PE array, wherein the encoding includes encoding a signed N-bit activation operand as a signed N-M bit higher order portion representing an integer value [signed {aN-1 . . . aN-M}+aN-1]*2M and a signed M+1 bit lower order portion representing an integer value signed {aNaN-M-1 . . . a0};
• and
• processing the encoded activation operand in the PE array, wherein the processing includes mathematically combining the encoded activation operand with a weight operand.