Edge couplers with coupling-assisting features

#The disclosure relates to photonics chips and, more specifically, to structures including an edge coupler and methods of forming such structures.

#Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip includes a photonic integrated circuit comprised of optical components, such as modulators, polarizers, and optical couplers, that are used to manipulate light received from a light source, such as an optical fiber or a laser.

#The light source may be coupled by an edge coupler, also known as a spot-size converter, to the photonic integrated circuit on the photonics chip. The edge coupler is configured to transfer light of a given mode from the light source to the photonic integrated circuit. The edge coupler may include an inverse taper having a tip that is positioned adjacent to an edge of a cavity in which the light source is situated. The gradually-varying cross-sectional area of the inverse taper supports mode transformation and mode size variation associated with mode conversion when light is transferred from the light source to the edge coupler.

#The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

#FIG. 1 is a top view of a structure at an initial fabrication stage of a processing method in accordance with embodiments of the invention.

#FIG. 2 is a cross-sectional view taken generally along line 2-2 in FIG. 1.

#With reference to FIGS. 1, 2, 2A and in accordance with embodiments of the invention, a structure 10 for a photonics chip includes a waveguide core 12 that is positioned on, and over, a dielectric layer 14 and a semiconductor substrate 16. In an embodiment, the dielectric layer 14 may be comprised of a dielectric material, such as silicon dioxide, and the semiconductor substrate 16 may be comprised of a semiconductor material, such as single-crystal silicon. In an embodiment, the dielectric layer 14 may be a buried oxide layer of a silicon-on-insulator substrate. The waveguide core 12 is separated from the semiconductor substrate 16 by the dielectric material of the intervening dielectric layer 14. The dielectric layer 14 adjoins the semiconductor substrate 16 along an interface, and the dielectric layer 14 has an upper surface on which the waveguide core 12 is positioned. In an alternative embodiment, one or more additional dielectric layers comprised of, for example, silicon dioxide may be positioned between the waveguide core 12 and the upper surface of the dielectric layer 14.

#In an embodiment, the waveguide core 12 may be comprised of a material having a refractive index that is greater than the refractive index of silicon dioxide. In an embodiment, the waveguide core 12 may be comprised of a semiconductor material, such as single-crystal silicon, amorphous silicon, or polysilicon. In an alternative embodiment, the waveguide core 12 may be comprised of a dielectric material, such as silicon nitride, silicon oxynitride, or aluminum nitride. In alternative embodiments, other materials, such as a III-V compound semiconductor, may be used to form the waveguide core 12.

#In an embodiment, the waveguide core 12 may be formed by patterning a layer with lithography and etching processes. In an embodiment, an etch mask may be formed by a lithography process over the layer, and unmasked sections of the layer may be etched and removed with an etching process. The masked sections of the layer may determine the patterned shape of the waveguide core 12. In an embodiment, the waveguide core 12 may be formed by patterning the semiconductor material (e.g., single-crystal silicon) of the device layer of a silicon-on-insulator substrate. In an embodiment, the waveguide core 12 may be formed by patterning a deposited layer comprised of its constituent material (e.g., silicon nitride).