Semiconductor package

A semiconductor package comprising:

• a first semiconductor package which comprises a first redistribution structure, a memory chip on a lower surface of the first redistribution structure, a passive component spaced apart from the memory chip on the lower surface of the first redistribution structure, a first encapsulant on at least a portion of each of the memory chip and the passive component, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant;
• and
• a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a logic chip on the third redistribution structure, and a second encapsulant on at least a portion of the logic chip,
• wherein each of the memory chip, the passive component, and the conductive post is electrically connected to the logic chip through the first redistribution structure and the third redistribution structure.

A semiconductor package comprising:

• a first redistribution structure;
• a first semiconductor chip on a lower surface of the first redistribution structure;
• a passive component on the lower surface of the first redistribution structure and spaced apart from the first semiconductor chip;
• a first encapsulant on at least a portion of each of the first semiconductor chip and the passive component;
• a second redistribution structure on the first encapsulant;
• a conductive post that electrically connects the first redistribution structure and the second redistribution structure through the first encapsulant;
• a second semiconductor chip on an upper surface of the first redistribution structure;
• and
• a second encapsulant on at least a portion of the second semiconductor chip,
• wherein the first encapsulant integrally covers each of a lower surface of the first semiconductor chip, a side surface of the first semiconductor chip, a lower surface of the passive component, and a side surface of the passive component.