US 2026/0011701 A1 · BYPASS INTERCONNECTIONS FOR STACKED SEMICONDUCTOR SYSTEMS

Abstract

Methods, systems, and devices for bypass interconnections for stacked semiconductor systems are described. An interface between a logic component and a system substrate of a semiconductor system may extend beyond an active area of a memory stack and couple between the logic component and the system substrate via one or more bypass regions. In some examples, through-silicon vias may be formed through portions of a memory stack, such as a semiconductor extension at edges of each memory die, which may be used for transfer of high-speed or high-energy signals. Additionally, or alternatively, a logic component may be placed on top of a stack of memory dies with separate bypass components along one or more sides adjacent to a memory stack, through which bypass interconnects may be formed, allowing for different configurations and avoiding the use of memory component silicon being allocated for such interconnections.

Claims30

Dependent claims

A semiconductor system, comprising:

a system substrate comprising a plurality of first conductors and a plurality of second conductors;
one or more first semiconductor components bonded with the system substrate and comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays, the interface circuitry coupled with the plurality of first conductors through the bonding between the one or more first semiconductor components and the system substrate;
and
a second semiconductor component bonded with the one or more first semiconductor components, the one or more first semiconductor components being between the second semiconductor component and the system substrate, the second semiconductor component comprising logic circuitry coupled with the interface circuitry through the bonding between the second semiconductor component and the one or more first semiconductor components, and that is coupled with the plurality of second conductors via a plurality of third conductors through the one or more first semiconductor components that bypass the interface circuitry.

1 more element

A semiconductor system, comprising:

a system substrate comprising a plurality of first conductors and a plurality of second conductors;
one or more first semiconductor components bonded with the system substrate and comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays, the interface circuitry coupled with the plurality of first conductors through the bonding between the one or more first semiconductor components and the system substrate;
one or more bypass components bonded with the system substrate and comprising a plurality of third conductors coupled with the plurality of second conductors through the bonding between the one or more bypass components and the system substrate;
and
a second semiconductor component bonded with the one or more first semiconductor components and with the one or more bypass components, the one or more first semiconductor components and the one or more bypass components being between the second semiconductor component and the system substrate, the second semiconductor component comprising logic circuitry that is coupled with the interface circuitry through the bonding between the second semiconductor component and the one or more first semiconductor components and that is coupled with the plurality of third conductors through the bonding between the one or more bypass components and the second semiconductor component.

2 more elements

A method of forming a semiconductor system, comprising:

bonding one or more first semiconductor components with a system substrate, the system substrate comprising a plurality of first conductors and a plurality of second conductors, the one or more first semiconductor components comprising one or more memory arrays and interface circuitry for accessing the one or more memory arrays, and bonding the one or more first semiconductor components with the system substrate comprising coupling the interface circuitry with the plurality of first conductors;
bonding a second semiconductor component with the one or more first semiconductor components, the one or more first semiconductor components being between the second semiconductor component and the system substrate, the second semiconductor component comprising logic circuitry, and bonding the second semiconductor component with the one or more first semiconductor components comprising coupling the logic circuitry with the interface circuitry;
and
coupling the logic circuitry with the plurality of second conductors via a plurality of third conductors through the one or more first semiconductor components that bypass the interface circuitry.