Redundant bond pads in stacked semiconductor architectures
AssigneeMicron Technology, Inc.
InventorsBharat Bhushan, Kunal R. Parekh, Lars P. Heineck, Akshay N. Singh
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AssigneeMicron Technology, Inc.
InventorsBharat Bhushan, Kunal R. Parekh, Lars P. Heineck, Akshay N. Singh
Estimating the term…
Methods, systems, and devices for redundant bond pads in stacked semiconductor architectures are described. A semiconductor device may be formed one or more redundant structures. A memory chip and a logic die may be formed with a redistribution layer that interconnects multiple bonding pads together. The redistribution layer may couple the bonding pads with a common via, where the common via interfaces with circuitry of a respective device. Additionally, or alternatively, a memory chip and a logic die may be formed with redundant via paths that form parallel electrical paths. The redundant via paths may couple device circuitry with respective bonding pads of a device. The memory chip and the logic die may be bonded together to form a semiconductor device.
A semiconductor device, comprising:
A method of manufacturing a semiconductor device, comprising:
A semiconductor device, comprising:
A method of manufacturing a semiconductor device, comprising:
Dependencies are inferred from the claim text.