Method of manufacturing semiconductor package and semiconductor package

A method of manufacturing a semiconductor package, the method comprising:

• disposing substrate strips on a lower mold, a plurality of semiconductor chips being arranged on the substrate strips, the substrate strips being on opposite sides of an injection hole at least partially defined by the lower mold;
• providing a release film on an upper mold, a first encapsulant being attached to the release film;
• allowing the upper mold and the lower mold to be proximate to each other such that the first encapsulant is aligned on the substrate strips;
• injecting a second encapsulant through the injection hole;
• and
• forming a first encapsulating layer and a second encapsulating layer by heating a space at least partially defined between the lower mold and the upper mold, the first encapsulating layer and the second encapsulating layer being stacked on the substrate strips,
• wherein the first encapsulating layer is formed by the first encapsulant flowing in a direction toward the lower mold, and
• the second encapsulating layer is formed by the second encapsulant flowing toward the opposite sides of the injection hole.

A method of manufacturing a semiconductor package, the method comprising:

• disposing a substrate strip on a lower mold, the substrate strip having plurality of semiconductor chips arranged thereon;
• providing a release film on an upper mold, the release film having a first encapsulant attached thereto;
• allowing the upper mold and the lower mold to be proximate to each other such that the first encapsulant is adjacent to the plurality of semiconductor chips;
• injecting a second encapsulant into a space at least partially defined between the upper mold and the lower mold;
• allowing the first encapsulant and the second encapsulant to simultaneously flow;
• and
• forming a first encapsulating layer and a second encapsulating layer in which the first encapsulant and the second encapsulant are cured, respectively,
• wherein an interface between the first encapsulating layer and the second encapsulating layer extends in a direction intersecting a side surface of the plurality of semiconductor chips.