Memory device including a plurality of ground selection transistors

A memory device comprising:

• a substrate;
• a first cell string between a first bit line and a common source line, the first cell string including a first string selection transistor connected to a first string selection line and a plurality of first ground selection transistors connected to a plurality of ground selection lines, wherein the plurality of first ground selection transistors are stacked on the substrate;
• and
• a second cell string between the first bit line and the common source line, the second cell string including a second string selection transistor connected to a second string selection line and a plurality of second ground selection transistors connected to the plurality of ground selection lines, wherein the plurality of second ground selection transistors are stacked on the substrate,
• wherein, when the first cell string is a selected cell string,
• the memory device is configured to apply a first on-voltage to a first ground selection line and a second ground selection line among the plurality of ground selection lines,
• a first subset of ground selection transistors, connected to the first ground selection line and the second ground selection line, among the plurality of second ground selection transistors are configured to be turned off based on the first on-voltage of the first ground selection line and the second ground selection line, and
• at least one ground selection transistor between the first subset of ground selection transistors is configured to be turned on.

A memory device comprising:

• a substrate;
• a plurality of lower ground selection lines stacked on the substrate;
• a plurality of upper ground selection lines stacked on the plurality of lower ground selection lines;
• and
• a plurality of cell strings connected between a first bit line and a common source line,
• wherein each cell string of the plurality of cell strings includes:
• a plurality of lower ground selection transistors connected to the plurality of lower ground selection lines;
• and
• a plurality of upper ground selection transistors connected to the plurality of upper ground selection lines,
• wherein, when a first cell string among the plurality of cell strings is a selected cell string,
• the memory device is configured to apply a first on-voltage to at least one lower ground selection line among the plurality of lower ground selection lines, and
• the memory device is configured to apply the first on-voltage to at least one upper ground selection line among the plurality of upper ground selection lines, and
• wherein, when the first cell string is the selected cell string, in each cell string of the plurality of cell strings other than the first cell string,
• at least one lower ground selection transistor connected to the at least one lower ground selection line among the plurality of lower ground selection transistors is configured to be turned off,
• at least one upper ground selection transistor connected to the at least one upper ground selection line among the plurality of upper ground selection transistors is configured to be turned off, and
• a plurality of ground selection transistors between the at least one lower ground selection transistor and the at least one upper ground selection transistor are configured to be turned on.