Methods and systems for clock control logic cloning for mesh clock

A system comprising:

• a processor;
• and
• a memory storing instructions executed by the processor to cause the processor to:
• generate a first clock path, wherein a first clock control logic (CCL) is connected between a mesh and a first sequential gate;
• disconnect the first CCL from the first sequential gate in the first clock path, and connecting the mesh to the first sequential gate;
• generate a second clock path, wherein the mesh is connected to a second CCL;
• generate a first clock tree in the first clock path, the first clock tree being connected to the first sequential gate, and connecting the first CCL between the mesh and the first clock tree;
• and
• generate a second clock tree in the second clock path between the second CCL and a second sequential gate.

A circuit, comprising:

• a mesh configured to receive a clock input;
• a block connected to the mesh, the block comprising at least at a first clock path and a second clock path,
• wherein the first clock path comprises:
• a first clock control logic (CCL);
• a first clock tree connected to the first CCL;
• and
• a first sequential gate connected to the first clock tree, and
• wherein the second clock path comprises:
• a second CCL;
• a second clock tree connected to the second CCL;
• and
• a second sequential gate connected to the second clock tree.