DESIGN TOOL FOR CONNECTING PORTS OF A NETWORK-ON-CHIP (NoC) VIA REGULAR EXPRESSIONS

A design tool for using regular expressions for mapping connectivity of ports for a network-on-chip (NoC), the design tool comprising a non-transitory computer readable medium for storing code, which when executed by one or more processors of the design tool, would cause the design tool to:

• receive a first regular expression that is used for selection of a first plurality of ports of the NoC;
• receive a second regular expression that is used for selection of a second plurality of ports to be connected to the first plurality of ports;
• execute, using the design tool, the first regular expression and the second regular expression to identify connections for the first plurality of ports to the second plurality of ports;
• present suggested connections for a user on a graphical user interface in regular expression based on the execute;
• determine if any first port of the first plurality of ports are connected to more than one second port of the second plurality or ports, wherein if any first port has multiple connections, then the design tool prevents the selection of the suggested connections;
• and
• allow the user to confirm the suggested connections if each of the first plurality of ports are connected to only one of the second plurality of ports such that there is no multiple connections.