Methods, systems, and computer readable media for scheduled traffic generation and transmission in electronics design automation (eda) test environments

A system for scheduled traffic generation in an electronics design automation (EDA) test environment, the system comprising:

• a computing platform including at least one processor and a memory;
• a test controller implemented by the at least one processor for receiving at least one parameter associated with a scheduled transmission of emulated network traffic to an electronics design under test, receiving a timestamp T0 in an EDA emulator timing domain, computing, based on the timestamp T0 in the EDA emulator timing domain and the at least one parameter, a traffic launch timestamp in the EDA emulator timing domain;
• and
• an EDA test platform for receiving the traffic launch timestamp, communicating the traffic launch timestamp and at least one test packet to the EDA emulator and receiving, from the EDA emulator, an indication as to whether the EDA emulator successfully initiated transmission of the at least one test packet to an electronics design under test at a time indicated by the traffic launch timestamp.

One or more non-transitory computer readable media having stored thereon executable instructions that when executed by one or more processors of one or more computer control the one or more computers to perform steps comprising:

• receiving, by a test controller, at least one parameter associated with a scheduled transmission of emulated network traffic to an electronics design under test;
• receiving, by the test controller and from an electronics design automation (EDA) test platform, a timestamp T0 in an EDA emulator timing domain;
• computing, by the test controller and based on the timestamp T0 in the EDA emulator timing domain and the at least one parameter, a traffic launch timestamp in the EDA emulator timing domain;
• communicating the traffic launch timestamp and at least one test packet to the EDA emulator;
• and
• receiving, from the EDA emulator, an indication as to whether the EDA emulator successfully initiated transmission of the at least one test packet to an electronics design under test at a time indicated by the traffic launch timestamp.