Design tool for using sub-architectures of a main architecture in network-on-ship design distribution and assembly
AssigneeArteris, Inc.
InventorChristopher PEZLEY
Life of this patent
Estimating the term…
Abstract
A design tool is disclosed for receiving constraints and parameters for an architecture to be synthesized for a network-on-chip (NoC) The design tool partitions the architecture into new a number of project elements (e.g. an architecture). The design tool removes these partitions of architectures from the current master file representation of the whole project architecture and saves the partitioned portions to the new sub-projects. The design tool copies any dependencies detected (e.g. if there is an external protocol defined and the architecture uses it) into the new sub-projects, such that each new sub-project is self-contained.
Claims14
A design tool for management of an architecture design the design tool comprising a non-transitory computer readable medium for storing code, which when executed by one or more processors of the design tool, would cause the design tool to:
- receive a project having a plurality of sub-architecture files;
- remove a set of sub-architecture files from the plurality of sub-architecture files;
- generate a sub-project for each of the set of sub-architecture files, wherein each sub-project includes all dependencies associated with a respective sub-architecture file so that the sub-project is self-contained;
- generate a plurality of folders, one for each sub-project, wherein each folder includes a configurable path to an external master project,
- wherein the design tool makes an external reference to any folder of the plurality of folders and import the plurality of folder at any moment in time to capture current state of the sub-project, thereby allowing a designer to view the project as a whole.
A design tool using a custom subnetwork description to generate a deadlock free network-on-chip (NoC), the design tool comprising a non-transitory computer readable medium for storing code, which when executed by one or more processors of the design tool, would cause the design tool to:
- identify a region within a floorplan of the NoC;
- generate a subnetwork that is optimally placed within the region;
- generate a configuration to a new NoC by synthesizing the NoC that includes the subnetwork;
- and
- select, using a configuration selection module, a final configuration to be implemented for the new NoC.
A method for synthesis of a network-on-chip (NoC) from a plurality architecture projects, the method comprising:
- receiving a project for the NoC, at a design tool, wherein the projects includes the plurality of architecture projects and a plurality of protocols associated with the plurality of architecture projects;
- associated at least one protocol with the protocol's respective architecture project;
- generate a plurality of folders, one for each architecture project, wherein each folder includes an external configurable path to the project;
- wherein the design tool makes an external reference to any folder of the plurality of folders and imports any one or more of the plurality of folder at any moment in time to capture current state of the plurality of architecture project associated with a respective folder, thereby allowing a designer to view the project as a whole.
Dependencies are inferred from the claim text.