Chiplet Hub with Multi-Unit Accessible HBM

A system comprising:

• a high bandwidth memory (HBM) having sides and two faces, a first face including connections for providing signals from the HBM;
• a chiplet hub die, the chiplet hub die having two faces and at least three sides, with a first face of the chiplet hub die including connections for the signals from the HBM and a second face including connections for mating with a substrate, the HBM mounted on the chiplet hub die, the first face of the HBM mating with the first face of the chiplet hub die so that the connections on the HBM first face cooperate with the connections on the chiplet hub die first face, the chiplet hub die including:
• at least one memory controller coupled to the connections on the chiplet hub die first face;
• a plurality of die-to-die (D2D) connection regions on the at least three sides for connecting to child chiplets capable of accessing memory;
• and
• logic coupled to the D2D connection regions and the at least one memory controller to allow at least two child chiplets connected to the D2D connection regions to access the mounted HBM;
• at least two child chiplets, each child chiplet including a D2D connection region for connecting to the chiplet hub die and logic for accessing the mounted HBM;
• and
• connections between the D2D connection regions of the at least two child chiplets and respective D2D connection regions of the chiplet hub die.