Chiplet Hub Providing Multiple Isolated Interconnect Types

A system comprising:

• a plurality of memories selected from an embedded memory, a die-to-die (D2D) chiplet connected memory and a high bandwidth memory (HBM), the HBM having sides and two faces, a first face including connections for providing signals from the HBM;
• a plurality of computational elements selected from an embedded compute unit, a D2D compute chiplet, a D2D I/O chiplet for connection to an external compute unit and a D2D accelerator chiplet;
• and
• a chiplet hub, the chiplet hub having two faces and at least three sides, the chiplet hub including:
• a plurality of D2D connection regions on the at least three sides, each D2D connection region for connection to one of D2D chiplet connected memory, D2D compute chiplet, D2D I/O chiplet for connection to an external compute unit and D2D accelerator chiplet;
• internal resources including:
• an embedded memory when the plurality of memories includes an embedded memory;
• and
• an embedded compute unit when the plurality of computational elements includes an embedded compute unit;
• connections for the signals from the HBM on a first face of the chiplet hub when the plurality of memories includes an HBM;
• and
• logic coupled to the plurality of D2D connection regions, any internal resources and any HBM for controlling access to and by D2D connected chiplets, any internal resources and any HBM,
• wherein each of the plurality of memories, the plurality of computational elements and the internal resources provide and receive transactions, and
• wherein the logic for controlling access to and by connected chiplets, any internal resources and any HBM includes logic for routing transactions between selected of the plurality of memories and the plurality of computational elements to form a plurality of simultaneously present, isolated system instances.