Caching host memory address translation data in a memory sub-system

A method comprising:

• buffering, within a set of request staging queues of an address translation circuit, address translation requests received from host interface circuits;
• storing, within a set of pending response queues, respective address translation requests, in an order received, that are waiting for an address translation from a host system;
• reordering, within a set of reordering buffers, address translations according to the order of the address translation requests maintained within the set of pending response queues;
• and
• storing, in a cache, a plurality of the address translations associated with the address translations requests and received from the host system.

A system comprising:

• a plurality of host interface circuits to interact with a host system;
• and
• an address translation circuit to handle address translation requests from the plurality of host interface circuits, the address translation circuit comprising:
• a set of request staging queues to buffer the address translation requests received from one of the plurality of host interface circuits;
• a set of reordering buffers to reorder address translations, which are to be supplied to the plurality of host interface circuits, according to an order of corresponding address translation requests received within the set of request staging queues;
• a cache coupled to the set of reordering buffers;
• and
• translation logic coupled to the set of reordering buffers and the cache, the translation logic to:
• store, in the cache, a plurality of the address translations associated with the address translation requests;
• and
• reinsert, into the set of reordering buffers, a first address translation from the cache for a subsequent request for the first address translation.