Cxl switch supporting low latency cache coherence, cxl computing system, and operating method thereof
AssigneeKorea Advanced Institute of Science and Technology
InventorsMyoungsoo JUNG, Miryeong KWON, Sangwon LEE, Donghyun GOUK
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Abstract
Disclosed is a CXL computing system including a compute express link (CXL)-enabled host CPU, CXL devices, and a CXL switch connecting the host CPU and the CXL devices. The CXL switch includes a switch coherence agent that manages cache coherence of the CXL devices connected to a lower layer.
Claims18
A CXL computing system comprising:
- a compute express link (CXL)-enabled host CPU;
- CXL devices;
- and
- a CXL switch connecting the host CPU and the CXL devices,
- wherein the CXL switch includes a switch coherence agent that manages cache coherence of the CXL devices connected to a lower layer.
An operating method of a CXL switch connected to a compute express link (CXL)-enabled host CPU and CXL devices, comprising:
- receiving a CXL message including a cache line request from a specific CXL device connected to a lower layer;
- checking whether there is at least one target device having a requested cache line in a cache among the CXL devices and the host CPU;
- and
- acquiring data from the target device to deliver the data to the specific CXL device when there is the target device.
A CXL switch implemented to connect a compute express link (CXL)-enabled host CPU and CXL devices, and manage cache coherence of the CXL devices connected to a lower layer through a switch coherence agent.
Dependencies are inferred from the claim text.