Processor and operation control method of processor

An operation control method of a processor including:

• a plurality of execution circuits configured to execute a plurality of computational instructions;
• a first instruction queue configured to hold the plurality of computational instructions;
• a plurality of second instruction queues respectively provided corresponding to the plurality of execution circuits, the plurality of second instruction queues being configured to hold the plurality of computational instructions transferred from the first instruction queue, and issue the plurality of computational instructions held in the second instruction queues to the corresponding execution units;
• a plurality of data buffers respectively provided corresponding to the plurality of execution circuits and configured to hold data to be used by the plurality of computational instructions;
• and
• a transfer control circuit, the operation control method comprising:
• detecting, by the transfer control circuit, an address of a memory that holds data used by each of the plurality of computational instructions held in the first instruction queue, transfer, to a second instruction queue corresponding to one of the plurality of execution circuits among the plurality of second instruction queues, target computational instructions that use data at a same address among the plurality of computational instructions, based on the detected address;
• and
• transferring, by the transfer control circuit, the data at the same address to a data buffer corresponding to the one of the plurality of execution circuits among the plurality of data buffers.