Memory prefetch mechanism based on instruction sets
AssigneeQUALCOMM Incorporated
InventorsSachin KUMAR, Saravana Raj SHANMUGAM, Kaustubh SARWATE
Life of this patent
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Abstract
Aspects of the disclosure are directed to batch memory prefetching. In accordance with one aspect, the disclosure includes examining a current cache line from a plurality of cache lines; determining if a conditional branch opcode or an unconditional branch opcode is present; sending an anticipatory address to a bulk memory to fetch one or more anticipatory program instructions; and depositing the one or more anticipatory program instructions into a prefetch cache memory to augment an initial set of program instructions.
Claims20
An apparatus comprising:
- an instruction sequencer configured to determine if a conditional branch opcode or an unconditional branch opcode is present and to anticipate a current prefetch buffer line based on a presence of the conditional branch opcode or the unconditional branch opcode;
- a prefetcher coupled to the instruction sequencer, the prefetcher configured to retrieve program instructions;
- and
- a prefetch buffer coupled to the prefetcher, the prefetch buffer configured to store the current prefetch buffer line.
An apparatus for implementing batch memory prefetching, the apparatus comprising:
- means for examining a current cache line from a plurality of cache lines;
- means for determining if a conditional branch opcode or an unconditional branch opcode is present;
- means for sending an anticipatory address to a bulk memory to fetch one or more anticipatory program instructions;
- and
- means for depositing the one or more anticipatory program instructions into a prefetch cache memory to augment an initial set of program instructions.
A method comprising:
- examining a current cache line from a plurality of cache lines;
- determining if a conditional branch opcode or an unconditional branch opcode is present;
- sending an anticipatory address to a bulk memory to fetch one or more anticipatory program instructions;
- and
- depositing the one or more anticipatory program instructions into a prefetch cache memory to augment an initial set of program instructions.
Dependencies are inferred from the claim text.