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AssigneesTakeoka Lab Corporation, Tokyo Electron Limited
InventorsShozo TAKEOKA, Yoshio KINOSHITA
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Provided is a processor enabling assembly code of a direct-addressing conditional-jump subroutine to be reduced. The processor includes a logic circuit executing a conditional-jump instruction of assembly code, and logically configured to: store, into an index register, an index register number that is an index to a jump-destination effective address; store jump-destination effective addresses differing from one another, or address offsets to jump-destination effective addresses differing from one another, into plural reference registers, respectively; fetch and decode a conditional jump instruction that is one instruction that quotes the index register; and then execute (S1) acquiring a jump-destination effective address or an address offset from the reference register corresponding to the index register number of the content of the index register and (S2) setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the address offset, to a register serving as the program counter.
A processor including a logic circuit configured to execute a conditional jump instruction of assembly code under indirect addressing using plural registers including a program counter as a table, the processor being logically configured to execute, after storing, into an index register, an index register number that is an index to a jump-destination effective address, storing jump-destination effective addresses that differ from one another in memory space, or address offsets from a predetermined reference to jump-destination effective addresses that differ from one another, into plural reference registers, respectively, and fetching and decoding a conditional jump instruction that is one instruction that quotes the index register:
A non-transitory computer-readable recording medium on which is stored a program to cause a processor to function, the processor including a logic circuit configured to execute a conditional jump instruction of assembly code under indirect addressing using plural registers including a program counter as a table, the program causing the processor to execute, as an execution of a conditional jump instruction that is one instruction that quotes an index register in a situation that an index register number that is an index to a jump-destination effective address is stored into the index register, and jump-destination effective addresses that differ from one another in memory space, or address offsets from a predetermined reference to jump-destination effective addresses that differ from one another, are stored into plural reference registers, respectively:
A method for executing a conditional jump instruction of assembly code under indirect addressing, the method being implemented by a processor that includes a logic circuit configured by using plural registers including a program counter, the method comprising, as an execution of a conditional jump instruction that is one instruction that quotes an index register in a situation that an index register number that is an index to a jump-destination effective address is stored into the index register, and jump-destination effective addresses that differ from one another in memory space, or address offsets from a predetermined reference to jump-destination effective addresses that differ from one another, are stored into plural reference registers, respectively:
Dependencies are inferred from the claim text.