Memory devices and operation methods thereof, and memory systems and storage mediums
AssigneeYangtze Memory Technologies Co., Ltd.
InventorShu Xie
Life of this patent
Estimating the term…
Abstract
Examples of the present disclosure provide a memory device and an operation method thereof, a memory system and a storage medium. The memory device includes: a memory cell array, and a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit is configured to: before performing a power on reset operation, set all state information of a plurality of main memory areas in a page buffer to a normal state; in the process of performing the power on reset operation, match a second address of each of the plurality of main memory areas with a first address in a register; and determine, according to a match result, whether to modify state information of a respective main memory area in the page buffer to a fault state.
Claims20
A memory device, comprising:
- a memory cell array including main memory areas;
- and
- a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit includes:
- first page buffers configured to store state information of the main memory areas respectively, wherein the state information includes a first state and a second state;
- and
- a register configured to store a first address of a main memory area of the main memory areas in the second state, and wherein the peripheral circuit is configured to:
- before performing a power on reset operation, set all the state information of the main memory areas in the first page buffers to the first state;
- during the performing the power on reset operation, match a second address of a respective main memory area with the first address of the main memory area in the register;
- and
- in response to the second address of the respective main memory area matching the first address of the main memory area in the register, modify the state information of the respective main memory area corresponding to the second address in the first page buffers to the second state.
An operation method of a memory device, wherein the memory device comprises:
- a memory cell array;
- and
- a peripheral circuit coupled with the memory cell array, and wherein the operation method includes:
- before performing a power on reset operation, setting all state information that indicates states of main memory areas in the memory cell array and stored in the peripheral circuit to a first state, wherein the state information includes the first state and a second state;
- during the performing the power on reset operation, matching a second address of a respective main memory area with a first address stored in the peripheral circuit, wherein the first address is an address of the main memory area which is in the second state;
- and
- modifying, in response to the second address of the respective main memory area matching the first address of the main memory area in the peripheral circuit, the state information of the respective main memory area corresponding to the second address in the peripheral circuit to the second state.
A memory system, comprising:
- one or more memory devices, each of the one or more memory devices including:
- a memory cell array including main memory areas;
- and
- a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit includes:
- first page buffers configured to store state information of the main memory areas respectively, wherein the state information includes a first state and a second state;
- and
- a register configured to store a first address of the main memory area in the second state, and
- wherein the peripheral circuit is configured to:
- before performing a power on reset operation, set all the state information of the main memory areas in the first page buffers to the first state;
- during the performing the power on reset operation, match a second address of a respective main memory area with the first address of the main memory area in the register;
- and
- in response to the second address of the respective main memory area matching the first address of the main memory area in the register, modify the state information of the respective main memory area corresponding to the second address in the first page buffers to the second state;
- and
- a memory controller coupled with the one or more memory devices and configured to control the one or more memory devices.
Dependencies are inferred from the claim text.