Soft decoding in memory systems

A memory device comprising a memory cell array and a peripheral circuit, wherein the memory cell array comprises memory cells, and the peripheral circuit is configured to:

• receive a read command from a memory controller;
• store, based on the read command, first soft data in a first latch, second soft data in a second latch, and hard data in a third latch;
• and
• receive a first page transfer command from the memory controller, wherein the first page transfer command indicates a selected latch from the first latch, the second latch, or the third latch to transfer data in the selected latch to a cache latch.

A memory system, comprising:

• a memory device comprising a memory cell array, wherein the memory cell array comprises memory cells, and
• a memory controller coupled to the memory device, wherein the memory system is configured to perform operations comprising:
• sending, by the memory controller, a read command to the memory device;
• storing, by the memory device based on the read command, first soft data in a first latch, second soft data in a second latch, and hard data in a third latch;
• and
• sending, by the memory controller, a first page transfer command to the memory device, wherein the first page transfer command indicates a selected latch from the first latch, the second latch, or the third latch to transfer data in the selected latch to a cache latch.