US 2026/0010292 A1 · MEMORY DEVICE, MEMORY CONTROLLER, AND MEMORY SYSTEM INCLUDING THE SAME

Abstract

A memory device includes a memory cell array including a plurality of planes, a plurality of FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes, and a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.

Claims20

Dependent claims

A memory device comprising:

a memory cell array including a plurality of planes;
a plurality of first first-in first-out (FIFO) memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes;
and
a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output,
wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.

2 more elements

A memory system comprising:

a memory controller configured to generate an initial command-address and operation packets respectively corresponding to a plurality of planes;
and
a memory device configured to perform operations for the plurality of planes in response to the initial command-address and the operation packets,
wherein the memory device includes
a memory cell array including the plurality of planes that include
an initial plane, the initial plane including data, the memory device is configured to first output data of the initial plane, and
a normal plane, the normal plane including data, the normal plane having a plane order after the initial plane, the memory device is configured to output data of the normal plane after outputting data of the initial plane;
and
an input/output circuit configured to temporarily receive and store data stored in the initial plane and the normal plane, based on the initial command-address, and output data of an operation plane corresponding to the operation packet to the memory controller, based on the operation packet.

6 more elements

Dependencies are inferred from the claim text.

Memory device, memory controller, and memory system including the same

Life of this patent

Memory device, memory controller, and memory system including the same

Life of this patent

Abstract

Claims20