Controller and system for state compression in memory cell

Abstract

Disclosed is a controller and system for state compression in memory cell. The controller comprises a processor. In one embodiment, the processor is configured to set values of D bits, based on values of M bits. M is an integer greater than 0 and D is an integer greater than 0. The controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory. In another embodiment, the controller is configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, and the controller comprises a processor configured to determine values of the M bits based on the values of the D bits.

Dependencies are inferred from the claim text.