Power test system and system-on-chip including the same

Abstract

A power test system capable of performing a power test on a power management interface in a test mode and a system-on-chip including the same. The power test system according to an embodiment of the present disclosure includes: a target power test controller that generates a target power test mode signal indicating whether a target is in a test mode and target power test data provided to the target while a target test mode is activated; and a target power controller that receives a pure test mode signal indicating whether the target is in a pure test mode, the target power test mode signal and the target power test data, transmits preset data to the target when the pure test mode is activated, and transmits the target power test data to the target when both the pure test mode and the target test mode are activated.

Dependencies are inferred from the claim text.