Methods and devices for time domain adc sampling and filtering
AssigneeIntel Corporation
InventorsAmy WHITCOMBE, Peter KURAHASHI, Hechen WANG, Richard DORRANCE, Brent R. CARLTON
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Abstract
An analog to digital converter (ADC) circuit including: a voltage-controlled delay circuit (VCDC) configured to: sample a received analog signal based on an input clock signal to generate analog signal samples; generate an output signal representative of the input clock signal shifted in the time domain with a delay based on the analog signal samples; and a time to digital converter (TDC) coupled to the voltage-controlled delay circuit and configured to generate a digital output signal based on the output signal.
Claims20
An analog to digital converter (ADC) circuit comprising:
- a voltage-controlled delay circuit (VCDC) configured to:
- sample a received analog signal based on an input clock signal to generate analog signal samples;
- generate an output signal representative of the input clock signal shifted in time domain with a delay based on the analog signal samples;
- and
- a time to digital converter (TDC) coupled to the voltage-controlled delay circuit and configured to generate a digital output signal based on the output signal.
Dependencies are inferred from the claim text.