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AssigneeChengdu Sino Microelectronics Technology Co.,Ltd.
InventorsPintang KANG, Yuhang HE, Lei CHEN, Xing ZHU
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An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.
A method of correcting an error in a successive approximation register analog-to-digital converter (SAR ADC), comprising:
A successive approximation register analog-to-digital converter (SAR ADC), comprising a comparator, a clock or timing signal generator, a SAR logic module, and a time decision module, wherein the time decision module has an input terminal connected to an output terminal of the comparator, the time decision module has one or more output terminals connected to the clock or timing signal generator and SAR logic module, and the time decision module has a timing terminal connected to a trigger signal of the clock or timing signal generator.
Dependencies are inferred from the claim text.