Fast, low area self-test for read-only memory

A method for performing a fast read-only memory (ROM) signature test, comprising:

• resetting a signature register;
• performing a first read of ROM data from a desired final address of a ROM core utilizing an extended read cycle over multiple clock cycles;
• performing a first exclusive OR (XOR) operation of the ROM data retrieved during the first read with contents of the signature register using an XOR circuit;
• storing a result of the first XOR operation in the signature register;
• performing a second read of ROM data utilizing the extended read cycle, wherein an address read during the second read is a complement of the desired final address;
• performing a second XOR operation of the ROM data retrieved during the second read with the contents of the signature register using the XOR circuit;
• storing a result of the second XOR operation in the signature register;
• performing a third read of the ROM data from the desired final address of the ROM core utilizing an at-speed read cycle, the at-speed read cycle being performed during one clock cycle;
• performing a third XOR operation of the ROM data retrieved during the third read with the contents of the signature register using the XOR circuit;
• storing a result of the third XOR operation in the signature register;
• performing a fourth read of the ROM data utilizing the at-speed read cycle, wherein an address read during the fourth read is the complement of the desired final address;
• performing a fourth XOR operation of the ROM data retrieved during the fourth read with the contents of the signature register using the XOR circuit;
• and
• storing a result of the fourth XOR operation in the signature register as a final signature value, wherein the final signature value is a word comprised of all logic 0's if no errors have been detected during the fast ROM test.

A method for testing a read-only memory (ROM) device, comprising:

• performing a first read operation using an extended read cycle to access a first address in a ROM core, the extended read cycle being performed over multiple clock cycles;
• performing a second read operation using the extended read cycle to access a second address in the ROM core, wherein the second address is a complement of the first address;
• performing a third read operation using an at-speed read cycle to access the first address in the ROM core, the at-speed read cycle being performed over a single clock cycle;
• performing a fourth read operation using the at-speed read cycle to access the second address in the ROM core;
• combining data retrieved from each read operation to generate a final signature;
• and
• comparing the final signature to an expected value to determine if errors are present in the ROM core.