Execution of multiple programming operations using cache register release in a memory sub-system
AssigneeMicron Technology, Inc.
InventorsWalter Di Francesco, Violante Moschiano, Umberto Siciliani
Life of this patent
Estimating the term…
Abstract
Control logic in a memory device initiates a first programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. A programming status associated with the first programming operation is determined. In response to determining the programming status satisfies a condition, a first set of data associated with the first programming operation is caused to be released from a cache register prior to completion of the first programming operation. A second set of data associated with a second programming operation is caused to be stored in the cache register.
Claims20
A memory device comprising:
- a memory array comprising a set of memory cells;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- initiating a first programming operation to program a first portion of the memory array to a target programming level of a set of programming levels;
- determining a programming status associated with the first programming operation;
- in response to determining the programming status satisfies a condition, causing a first set of data associated with the first programming operation to be released from a cache register prior to completion of the first programming operation;
- and
- causing a second set of data associated with a second programming operation to be stored in the cache register.
A method comprising:
- initiating a first programming operation to program a first portion of memory cells of a memory device to a target programming level of a set of programming levels;
- determining a programming status associated with the first programming operation;
- in response to determining the programming status satisfies a condition, causing a first set of data associated with the first programming operation to be released from a cache register prior to completion of the first programming operation;
- and
- causing a second set of data associated with a second programming operation to be stored in the cache register.
A memory sub-system comprising:
- a memory device comprising a set of memory cells;
- and
- control logic, operatively coupled to the memory device, the control logic to perform operations comprising:
- initiating a first programming operation to program a first portion of the set of memory cells to a target programming level of a set of programming levels;
- determining a programming status associated with the first programming operation;
- in response to determining the programming status satisfies a condition, causing a first set of data associated with the first programming operation to be released from a cache register prior to completion of the first programming operation;
- and
- causing a second set of data associated with a second programming operation to be stored in the cache register.
Dependencies are inferred from the claim text.