Program time improvement for nand die with coarse bitscan during program-verify

A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes each connected to one of a plurality of bit lines, each of the plurality of bit lines coupled to one of a plurality of sense amplifiers arranged in tiers, the controller configured to:

• instruct the memory apparatus to program the memory cells in each of a plurality of program iterations of a program operation;
• instruct the memory apparatus to count a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the plurality of data states targeted for the memory cells in each of a plurality of verify iterations of the program operation, the count being a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.

A method of operating a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes each connected to one of a plurality of bit lines, each of the plurality of bit lines coupled to one of a plurality of sense amplifiers arranged in tiers, the method comprising the steps of:

• programing the memory cells in each of a plurality of program iterations of a program operation;
• and
• counting a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the plurality of data states targeted for the memory cells in each of a plurality of verify iterations of the program operation, the count being a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.