# US 2025/0385083 A1 · Methods and system for duty factor ramped timed ion implant matching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0385083 A1 - Document ID: US20250385083A1 - Status: Published application - Kind: A1 - Application number: 18/812,431 - Filed: 2024-08-22 - Published: 2025-12-18 - Earliest claimed: 2024-06-12 - Assignees: Applied Materials, Inc. - Applicants: Applied Materials, Inc. - Inventors: Vincent A. DENO; Richard G. APPEL, III; Cuiyang WANG; Deven Raj MITTAL; James R. MCLANE; Vikram M. BHOSLE - Web page: https://patentgrep.com/patent/US20250385083A1 ## CPC - H01J 37/32926: {Software, data control or modelling} - H01J 37/321: {the radio frequency energy being inductively coupled to the plasma} - H01J 37/32146: {Amplitude modulation, includes pulsing} - H01J 2237/3365: Plasma source implantation - H10P 30/20: into semiconductor materials, e.g. for doping - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein is a method for duty factor ramped timed ion implant matching. The method includes receiving, by a processing circuit, a duty cycle parameter from a user interface associated with the processing circuit. The method further includes generating, by the processing circuit, a control signal for a wafer pulse power supply of a plasma doping system to alter a pulse duty cycle of the wafer pulse power supply according to the duty cycle parameter. The method further includes sending, by the processing circuit, the control signal to the wafer pulse power supply to thereby alter a duty cycle of a pulse signal generated by the wafer pulse power supply. ## Claims ### Claim 1 A computer implemented method comprising: receiving, by a processing circuit, a duty cycle parameter from a user interface associated with the processing circuit; generating, by the processing circuit, a control signal for a wafer pulse power supply of a plasma doping system to alter a pulse duty cycle of the wafer pulse power supply according to the duty cycle parameter; and sending, by the processing circuit, the control signal to the wafer pulse power supply to thereby alter a duty cycle of a pulse signal generated by the wafer pulse power supply. ### Claim 2 (depends on 1) The computer implemented method of claim 1, wherein the duty cycle parameter includes a plurality of duty cycle parameters. ### Claim 3 (depends on 2) The computer implemented method of claim 2, wherein each of the plurality of duty cycle parameters includes a unique duty cycle ratio of the pulse signal that is selectable at the user interface. ### Claim 4 (depends on 2) The computer implemented method of claim 2, wherein the plurality of duty cycle parameters includes a first duty cycle parameter and one or more subsequent duty cycle parameters with increasing duty cycle. ### Claim 5 (depends on 1) The computer implemented method of claim 1, wherein the duty cycle parameter includes a predetermined number of pulses sent by the wafer pulse power supply, and wherein the method further comprises: maintaining, by the processing circuit, a counter of a number of pulses sent by the wafer pulse power supply; wherein the control signal is generated in response to the counter exceeding the predetermined number of pulses. ### Claim 6 (depends on 1) The computer implemented method of claim 1, wherein the duty cycle parameter includes a predetermined amount of time, and wherein the method further comprises: maintaining, by the processing circuit, a clock or timer; wherein the control signal is generated in response to the clock or timer indicating that the predetermined amount of time has passed. ### Claim 7 (depends on 1) The computer implemented method of claim 1, wherein the duty cycle parameter is selected such that the generated control signal causes the pulse duty cycle to generate a doping profile in an experimental wafer to match a predetermined doping profile. ### Claim 8 (depends on 1) The computer implemented method of claim 1, wherein the user interface is executed by a computer application of a computing device in communication with the processing circuit, the user interface having one or more selectable and alterable duty cycle parameter options. ### Claim 9 (depends on 1) The computer implemented method of claim 1, wherein the wafer pulse power supply is to provide a biasing voltage to a semiconductor wafer during a doping process thereof, the biasing voltage configured to provide sufficient energy to implant ions into the semiconductor wafer. ### Claim 10 A plasma doping system comprising: a memory having instructions stored thereon; a processing circuit to execute the instructions, which when executed by the processing circuit causes the processing circuit to; receive a duty cycle parameter from a user interface associated with the processing circuit; generate a control signal for a wafer pulse power supply of a plasma doping system to alter a pulse duty cycle of the wafer pulse power supply according to the duty cycle parameter; and send the control signal to the wafer pulse power supply to thereby alter a duty cycle of a pulse signal generated by the wafer pulse power supply. ### Claim 11 (depends on 10) The plasma doping system of claim 10, wherein the duty cycle parameter includes a plurality of duty cycle parameters; wherein each of the plurality of duty cycle parameters includes a unique duty cycle ratio of the pulse signal that is selectable at the user interface; and wherein the plurality of duty cycle parameters includes a first duty cycle parameter and one or more subsequent duty cycle parameters with increasing duty cycle. ### Claim 12 (depends on 10) The plasma doping system of claim 10, wherein the duty cycle parameter includes a predetermined number of pulses sent by the wafer pulse power supply, and wherein the processing circuit is further caused to: maintain a counter of a number of pulses sent by the wafer pulse power supply, wherein the control signal is generated in response to the counter exceeding the predetermined number of pulses. ### Claim 13 (depends on 10) The plasma doping system of claim 10, wherein the duty cycle parameter includes a predetermined amount of time, and wherein the processing circuit is further caused to: maintaining a clock or timer, wherein the control signal is generated in response to the clock or timer indicating that the predetermined amount of time has passed. ### Claim 14 (depends on 10) The plasma doping system of claim 10, wherein the user interface is generated by a computer application executed by the processing circuit, the user interface having one or more selectable and alterable duty cycle parameter options; and wherein the duty cycle parameter is selected from among the one or more selectable and alterably duty cycle parameter options such that the generated control signal causes the pulse duty cycle to generate a doping profile in an experimental wafer to match a predetermined doping profile. ### Claim 15 (depends on 10) The plasma doping system of claim 10, wherein the wafer pulse power supply is to provide a biasing voltage to a semiconductor wafer during a doping process thereof, the biasing voltage configured to provide sufficient energy to implant ions into the semiconductor wafer. ### Claim 16 A non-transitory computer-readable storage medium having executable instructions stored thereon, which when executed by a processing circuit causes the processing circuit to: receive a duty cycle parameter from a user interface associated with the processing circuit; generate a control signal for a wafer pulse power supply of a plasma doping system to alter a pulse duty cycle of the wafer pulse power supply according to the duty cycle parameter; and send the control signal to the wafer pulse power supply to thereby alter a duty cycle of a pulse signal generated by the wafer pulse power supply. ### Claim 17 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the wafer pulse power supply is to provide a biasing voltage to a semiconductor wafer during a doping process thereof, the biasing voltage configured to provide sufficient energy to implant ions into the semiconductor wafer; wherein the duty cycle parameter includes a plurality of duty cycle parameters; wherein each of the plurality of duty cycle parameters includes a unique duty cycle ratio of the pulse signal that is selectable at the user interface; and wherein the plurality of duty cycle parameters includes a first duty cycle parameter and one or more subsequent duty cycle parameters with increasing duty cycle. ### Claim 18 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the duty cycle parameter includes a predetermined number of pulses sent by the wafer pulse power supply, and wherein the processing circuit is further caused to: maintain a counter of a number of pulses sent by the wafer pulse power supply, wherein the control signal is generated in response to the counter exceeding the predetermined number of pulses. ### Claim 19 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the duty cycle parameter includes a predetermined amount of time, and wherein the processing circuit is further caused to: maintain a clock or timer, wherein the control signal is generated in response to the clock or timer indicating that the predetermined amount of time has passed. ### Claim 20 (depends on 16) The non-transitory computer-readable storage medium of claim 16, wherein the user interface is generated by a computer application executed by the processing circuit, the user interface having one or more selectable and alterable duty cycle parameter options; and wherein the duty cycle parameter is selected from among the one or more selectable and alterably duty cycle parameter options such that the generated control signal causes the pulse duty cycle to generate a doping profile in an experimental wafer to match a predetermined doping profile.