# US 2025/0377902 A1 · Splash screen management in preboot environments > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0377902 A1 - Document ID: US20250377902A1 - Status: Published application - Kind: A1 - Application number: 18/734,935 - Filed: 2024-06-05 - Published: 2025-12-11 - Earliest claimed: 2024-06-05 - Assignees: Dell Products L.P. - Applicants: Dell Products L.P. - Inventors: Adolfo S. Montero; Ibrahim Sayyed; Laxmi Lavanya Medicherla - Web page: https://patentgrep.com/patent/US20250377902A1 ## CPC - G06F 9/4408: {Boot device selection} - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F 9/4411: {Configuring for operating with peripheral devices; Loading of device drivers} - G06F 9/54: Interprogram communication - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods for splash screen management in preboot environments. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a processor, and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the processor to: determine, by a Basic Input/Output System (BIOS) application, that a display driver of a Board Support Package (BSP) provided by a manufacturer of the processor; and send a message, from the BIOS application to the display driver, to replace a first splash screen with a second splash screen. ## Claims ### Claim 1 An Information Handling System (IHS), comprising: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the processor to: determine, by a Basic Input/Output System (BIOS) application, that a display driver of a Board Support Package (BSP) provided by a manufacturer of the processor; and send a message, from the BIOS application to the display driver, to replace a first splash screen with a second splash screen. ### Claim 2 (depends on 1) The IHS of claim 1, wherein the message instructs the display driver to replace contents of a framebuffer where the first splash screen is stored. ### Claim 3 (depends on 1) The IHS of claim 1, wherein the first splash screen comprises an image provided by the SoC manufacturer. ### Claim 4 (depends on 1) The IHS of claim 1, wherein the second splash screen comprises an image provided by an Original Equipment Manufacturer (OEM) of the IHS. ### Claim 5 (depends on 1) The IHS of claim 1, wherein to determine the display driver is installed, the program instructions, upon execution, cause the processor to access, via the BIOS application, a device tree that describes hardware interfaces and peripherals in the IHS. ### Claim 6 (depends on 1) The IHS of claim 1, wherein the program instructions, upon execution, cause the processor to send the message, via the BIOS application, during a Boot Device Selection (BDS) phase of a boot sequence. ### Claim 7 (depends on 1) The IHS of claim 1, wherein the program instructions, upon execution, cause the processor to select, via the BIOS application, the second splash screen among a plurality of splash screens based, at least in part, upon a policy. ### Claim 8 (depends on 7) The IHS of claim 7, wherein the BIOS application is configured to send the message, at least in part, based upon at least one of: a location of the IHS, or a determination of whether the IHS is in factory service mode. ### Claim 9 (depends on 1) The IHS of claim 1, wherein the program instructions, upon execution, cause the processor to select, via the BIOS application, the second splash screen among a plurality of splash screens based, at least in part, upon a user selection during a previous boot of the IHS. ### Claim 10 (depends on 1) The IHS of claim 1, wherein the program instructions, upon execution, cause the processor to render the second splash screen in lieu of the first splash screen prior to launch of any host Operating System (OS). ### Claim 11 A method, comprising: determining, in a preboot environment, that a display driver of a Board Support Package (BSP) is installed; and in response to the determination, invoking an Application Programming Interface (API) call to replace a splash screen stored in a framebuffer. ### Claim 12 (depends on 11) The method of claim 11, wherein the preboot environment comprises a Boot Device Selection (BDS) phase of a boot sequence. ### Claim 13 (depends on 11) The method of claim 11, wherein the API call replaces a first splash screen comprising a first image provided by a System-on-Chip (SoC) manufacturer with a second splash screen comprising a second image provided by an Original Equipment Manufacturer (OEM). ### Claim 14 (depends on 13) The method of claim 13, further comprising invoking the API call based, at least in part, upon at least one of: a location of the SoC, or a determination of whether the SoC is in factory service mode. ### Claim 15 (depends on 11) The method of claim 11, further comprising rendering the replaced splash screen prior to the launch of any host Operating System (OS). ### Claim 16 A hardware memory device having program instructions stored thereon that, upon execution by a processor of an Information Handling System (IHS), cause the processor to: determine, in a preboot environment, that a display driver of a Board Support Package (BSP) is installed; and in response to the determination, invoke an Application Programming Interface (API) call to replace a splash screen. ### Claim 17 (depends on 16) The hardware memory device of claim 16, wherein the API call replaces a first splash screen comprising a first image provided by a first manufacturer with a second splash screen comprising a second image provided by a second manufacturer. ### Claim 18 (depends on 16) The hardware memory device of claim 16, wherein the preboot environment comprises a Boot Device Selection (BDS) phase of a boot sequence. ### Claim 19 (depends on 16) The hardware memory device of claim 16, wherein the processor is part of a heterogenous computing platform selected from the group consisting of: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), and an Application-Specific Integrated Circuit (ASIC). ### Claim 20 (depends on 19) The hardware memory device of claim 19, wherein the heterogenous computing platform comprises a Reduced Instruction Set Computer (RISC) processor coupled to the EC via an interconnect, and wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus.