Read clock generation for synchronous graphics random access memory
AssigneeMicron Technology, Inc.
InventorKevin GAJERA
Life of this patent
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Abstract
In some implementations, a memory apparatus including a synchronous graphics random access memory (SGRAM) associated with a first clock signal having a first clock frequency may receive a command to initiate a read clock. The memory apparatus may generate read clock data based on one or more control parameters stored to a mode register and a second clock signal having a second clock frequency that is double the first clock frequency. The memory apparatus may output a read clock signal that is based on the read clock data, the read clock signal having a third clock frequency that is double the second clock frequency, wherein the read clock signal is associated with a memory access command for the SGRAM.
Claims24
A system, comprising:
- synchronous graphics random access memory (SGRAM) associated with a first clock signal having a first clock frequency;
- a mode register configured to provide one or more control parameters for read clock generation associated with the SGRAM;
- a command address decoder configured to provide one or more command parameters associated with a memory access command for the SGRAM;
- a read clock control component configured to generate read clock data based on the one or more control parameters and a second clock signal having a second clock frequency that is double the first clock frequency;
- and
- a read clock generator configured to generate a read clock signal having a third clock frequency that is double the second clock frequency based on the read clock data and the second clock signal.
A system, comprising:
- a synchronous graphics random access memory (SGRAM) associated with a first clock signal having a first clock frequency;
- a mode register configured to provide one or more control parameters for read clock generation associated with the SGRAM;
- one or more combinational circuits configured to generate read clock data based on the one or more control parameters;
- a first serialization component configured to obtain a first portion of the read clock data from the one or more combinational circuits based on a second clock signal having a second clock frequency that is double the first clock frequency;
- a second serialization component configured to obtain a second portion of the read clock data from the one or more combinational circuits based on the second clock frequency;
- and
- a driver configured to:
- obtain, from the first serialization component, the first portion of the read clock data;
- obtain, from the second serialization component, the second portion of the read clock data;
- and
- output, based on the first portion of the read clock data and the second portion of the read clock data, a read clock signal having a third clock frequency that is double the second clock frequency.
A method, comprising:
- receiving, by a memory apparatus comprising a synchronous graphics random access memory (SGRAM) associated with a first clock signal having a first clock frequency, a command to initiate a read clock;
- generating, by the memory apparatus, read clock data based on one or more control parameters stored to a mode register and a second clock signal having a second clock frequency that is double the first clock frequency;
- and
- outputting, by the memory apparatus, a read clock signal that is based on the read clock data, the read clock signal having a third clock frequency that is double the second clock frequency, wherein the read clock signal is associated with a memory access command for the SGRAM.
Dependencies are inferred from the claim text.