Shared top level digital-to-analog parallel data bus

An integrated circuit comprising:

• N analog circuit blocks, each comprising at most X data registers;
• a bidirectional M-bit parallel data bus coupled to each of the N analog circuit blocks;
• an external data port configured to receive data external to the integrated circuit;
• an interface circuit coupled to the external data port and the bidirectional M-bit parallel data bus, the interface circuit comprising
• an analog circuit block selection output coupled to each of the N analog circuit blocks and configured to select an analog circuit block using at most N signals,
• a register selection output coupled to each of the N analog circuit blocks and configured to select a data register using log2X signals, the register selection output being a log2X-bit register address coupled to each of the N analog circuit blocks, and
• a mode selection output coupled to each of the N analog circuit blocks and configured to control the direction of data flow between the N analog circuit blocks and the interface circuit on the bidirectional M-bit parallel data bus;
• and
• a non-volatile memory (NVM) coupled to the interface circuit and configured to read and write configuration data to and from selected data registers of selected analog circuit blocks over the bidirectional M-bit parallel data bus.

A method of transferring configuration data between an interface circuit of an integrated circuit and a data register of an analog circuit block, the method comprising:

• selecting a first analog circuit block from N analog circuit blocks of the integrated circuit by asserting at most N block selection signals at an analog circuit block selection output of the interface circuit coupled to each of the N analog circuit blocks;
• selecting a first data register from at most X data registers of the first analog circuit block by asserting at most X block selection signals at a register selection output of the interface circuit coupled to each of the N analog circuit blocks;
• enabling a data output of the interface circuit coupled to a bidirectional M-bit parallel data bus to transmit first configuration data over the bidirectional M-bit parallel data bus to the first analog circuit block, the bidirectional M-bit parallel data bus being coupled to each of the N analog circuit blocks;
• and
• writing the first configuration data from the bidirectional M-bit parallel data bus to the first data register by asserting, after enabling the data output of the interface circuit, a write enable signal at a mode selection output of the interface circuit coupled to each of the N analog circuit blocks.