Systems and methods for monitoring an instruction bus
OwnerBarak Cherches, Clive David Bittlestone +1inventors
InventorsBarak Cherches, Clive David Bittlestone, Uri Weinrib
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Abstract
Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.
Claims20
A method comprising:
- storing entries in a first memory, wherein each entry of the entries specifies a respective address and a respective instruction;
- fetching a first instruction corresponding to a first entry of the entries to produce a first fetched instruction;
- comparing the first fetched instruction to the respective instruction of the first entry;
- and
- determining whether to fetch a second instruction based on determining whether a match exists between the first fetched instruction and the respective instruction of the first entry.
A system comprising:
- a processing core configurable to fetch fetched instructions;
- a bus;
- a first memory configurable to store entries, wherein each entry of entries specifies a respective address and a respective instruction;
- a hardware logic unit configurable to:
- compare the fetched instructions to the entries;
- and
- determine whether to reset the system based on determining whether there is a mismatch between a fetched instruction of the fetched instructions and an entry of the entries.
A system comprising:
- a memory configurable to store entries, wherein the entries correspond to respective functions;
- a hardware logic unit configurable to:
- monitor signals on a bus to determine fetched instructions;
- compare the fetched instructions to the entries;
- and
- determine whether to allow the system to continue operation based on determining whether a match exists between a fetched instruction of the fetched instructions and an entry of the entries.
Dependencies are inferred from the claim text.