US 2025/0366203 A1 · SEMICONDUCTOR STRUCTURE

Abstract

A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.

Claims20

Dependent claims

A semiconductor structure, comprising:

a plurality of transistors, each of the plurality of transistors comprising:
a base fin surrounded by an isolation structure,
channel members stacked one over another over the base fin, and
a gate structure wrapping around each of the channel members and extending along the isolation structure;
and
a plurality of metal layers disposed over the plurality of transistors,
wherein the plurality of metal layers comprises a first metal layer adjacent the plurality of transistors, a second metal layer over the first metal layer, and further metal layers over the second metal layer,
wherein the first metal layer comprises first metal layer structures,
wherein the second metal layer comprises second metal layer structures,
wherein a first thickness of the first metal layer structures is smaller than a second thickness of the second metal layer structures,
wherein one of the further metal layers comprises upper metal layer structures,
wherein a third thickness of the upper metal layer structures is smaller than the second thickness.

9 more elements

A semiconductor structure, comprising:

a substrate comprising a first doped well and a second doped well;
an isolation structure over the substrate;
a first transistor over the first doped well and comprising:
a first base fin extending from the first doped well and through the isolation structure,
first channel members stacked one over another over the first base fin, and
a first gate structure wrapping around each of the first channel members and extending along the isolation structure;
a second transistor over the second doped well and comprising:
a second base fin extending from the second doped well and through the isolation structure,
second channel members stacked one over another over the second base fin, and
a second gate structure wrapping around each of the second channel members and extending along the isolation structure;
and
a plurality of metal layers disposed over the first transistor and the second transistor,
wherein the plurality of metal layers comprises a first metal layer adjacent the first transistor and the second transistor, a second metal layer over the first metal layer, and further metal layers over the second metal layer,
wherein the first metal layer comprises first metal layer structures,
wherein the second metal layer comprises second metal layer structures,
wherein a first thickness of the first metal layer structures is smaller than a second thickness of the second metal layer structures,
wherein one of the further metal layers comprises upper metal layer structures,
wherein a third thickness of the upper metal layer structures is smaller than the second thickness.

15 more elements

A semiconductor structure, comprising:

a substrate comprising a first doped well and a second doped well;
an isolation structure over the substrate;
a first transistor over the first doped well and comprising:
a first base fin extending from the first doped well and through the isolation structure,
first channel members stacked one over another over the first base fin, and
a first gate structure wrapping around each of the first channel members and extending along the isolation structure;
a second transistor over the second doped well and comprising:
a second base fin extending from the second doped well and through the isolation structure,
second channel members stacked one over another over the second base fin, and
a second gate structure wrapping around each of the second channel members and extending along the isolation structure;
and
a plurality of metal layers disposed over the first transistor and the second transistor,
wherein the plurality of metal layers comprises a first metal layer adjacent the first transistor and the second transistor, a second metal layer over the first metal layer, and further metal layers over the second metal layer,
wherein the first metal layer comprises first metal layer structures,
wherein the second metal layer comprises second metal layer structures,
wherein a first thickness of the first metal layer structures is smaller than a second thickness of the second metal layer structures,
wherein one of the further metal layers comprises upper metal layer structures,
wherein a third thickness of the upper metal layer structures is smaller than the second thickness,
wherein the first gate structure and the second gate structure extend lengthwise along a direction,
wherein the first gate structure interfaces the second gate structure at an interface,
wherein top surfaces of the first base fin and the second base fin are higher than a top surface of the isolation structure.

18 more elements

Dependencies are inferred from the claim text.

Semiconductor structure

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Semiconductor structure

Life of this patent

Abstract

Claims20