Guard ring capacitor operating method

A method of biasing a guard ring structure, the method comprising:

• biasing a gate of the guard ring structure and a gate of a metal oxide semiconductor (MOS) transistor to a bias voltage level;
• and
• biasing first and second heavily doped regions of the guard ring structure and first and second source/drain (S/D) regions of the MOS transistor to a power domain voltage level, wherein
• each of the first and second S/D regions has a first doping type,
• each of the first and second heavily doped regions has a second doping type different from the first doping type, and
• each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

A method of biasing a guard ring structure, the method comprising:

• biasing a gate of the guard ring structure and a gate of a metal oxide semiconductor (MOS) transistor to a bias voltage level;
• and
• biasing first and second heavily doped regions of the guard ring structure and first and second source/drain (S/D) regions of the MOS transistor to a power domain voltage level, wherein
• each of the first and second S/D regions has a first doping type and extends in a substrate region having a second doping type different from the first doping type, and
• each of the first and second heavily doped regions surrounds the MOS transistor in the substrate region and has the second doping type.