Tag way-halting

A system for performing tag way halting comprising:

• a memory subsystem including a preamble tag memory and one or more prologue tag memories for one or more ways,
• wherein the preamble tag memory comprises:
• a preamble memory array, a preamble memory control circuit, a preamble memory wordline driver, a preamble memory input/output circuitry, and a preamble memory hit circuitry, wherein the preamble tag memory stores a first set of bits from a tag portion of a plurality of addresses stored at the memory subsystem, wherein the preamble memory hit circuitry performs a comparison of preamble bits of a received address and the stored first set of bits from the tag portion in the preamble tag memory, and
• wherein the one or more prologue tag memories each comprises a prologue memory array, a prologue memory control circuit, a prologue memory wordline driver, a prologue memory input/output circuitry, and a prologue memory hit circuitry, wherein the one or more prologue tag memories store a second set of bits from the tag portion and memory data information of the plurality of addresses, wherein the prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored second set of bits from the tag portion in that prologue tag memory.