Automated hardware-aware deployment of machine learning pipelines on chipsets
AssigneeSiMa Technologies, Inc.
InventorNaveen Kumar Sangeneni
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AssigneeSiMa Technologies, Inc.
InventorNaveen Kumar Sangeneni
Estimating the term…
A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.
A method for implementing a machine learning pipeline on a chip containing a plurality of hardware compute elements, the method comprising:
A device having a chipset comprising a plurality of processors, and a non-transitory computer-readable storage medium, having instructions encoded thereon that, when executed by the plurality of processors, cause at least one processor to:
Dependencies are inferred from the claim text.