US 2025/0359326 A1Published application

Integrated circuit, system and method of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsTe-Hsin CHIU, Wei-Cheng LIN, Wei-An LAI, Jiann-Tyng TZENG

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Abstract

An integrated circuit includes a first power rail on a back-side of a substrate, and extending in a first direction, a first and second flip-flop, and a first conductor on a first metal layer and extending in a second direction. The first flip-flop includes a first region that includes a first inverter, a second inverter having a first output pin, and a first input pin. The second flip-flop includes a second region that abuts the first region at a first boundary, and includes a third inverter, a fourth inverter having a second output pin, and a second input pin. The first conductor overlaps the first boundary, and electrically couples the first output pin and the second output pin together. The first and second flip-flop are on a front-side of the substrate. The first input pin is offset from the first boundary in the second direction.

Claims20

Dependent claims

An integrated circuit, comprising:

a set of power rails on a back-side of a substrate, and extending in a first direction, each power rail being separated from an adjacent power rail in a second direction different from the first direction;
a first flip-flop in a first region, the first flip-flop comprising:
a first set of conductors extending in the first direction, and being located on a first metal layer;
and
a first inverter having a first output terminal;
a second flip-flop being in a second region, the second region abutting the first region at a first boundary, the second flip-flop comprising:
a second set of conductors extending in the first direction, being located on the first metal layer, the second set of conductors being separated from the first set of conductors in the second direction;
and
a second inverter having a second output terminal;
and
a third flip-flop being in a third region, the third region abutting the second region at a second boundary, the third flip-flop comprising:
a third set of conductors extending in the first direction, being located on the first metal layer and being separated from the first set of conductors and the second set of conductors in the second direction;
and
a third inverter having a third output terminal;
and
a first conductor on a second metal layer above the first metal layer, extending in the second direction, overlapping the first boundary and the second boundary, and electrically coupling the first output terminal, the second output terminal and the third output terminal together, at least one of the first inverter, the second inverter or the third inverter being configured to output a first clock signal on the first conductor;
wherein the third set of conductors are offset from the second boundary in the second direction;
and
wherein the second region is between the first region and the third region.

16 more elements

An integrated circuit, comprising:

a first power rail on a back-side of a substrate, and extending in a first direction;
a first flip-flop coupled to at least the first power rail, and including a first region, the first region comprising:
a first inverter coupled to the first power rail;
a second inverter having a first output pin, and being coupled to the first inverter;
and
a first input pin coupled to the first inverter, and extending in the first direction;
a second flip-flop coupled to at least the first power rail, and including a second region, the second region abutting the first region at a first boundary, and comprising:
a third inverter coupled to the first power rail;
a fourth inverter having a second output pin, and being coupled to the third inverter;
and
a second input pin coupled to the third inverter, and extending in the first direction;
and
a first conductor on a first metal layer, extending in a second direction different from the first direction, overlapping the first boundary, and electrically coupling the first output pin and the second output pin together, at least one of the second inverter or the fourth inverter being configured to output a clock signal on the first conductor;
wherein the first flip-flop and the second flip-flop are on a front-side of the substrate opposite from the back-side;
and
wherein the first input pin is offset from the first boundary in the second direction.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/286,643Filed 31 Jul 2025
Priority: 30 Apr 2020
Published: 20 Nov 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H03K 3/35625
Of the primary-secondary type: using complementary field-effect transistors
H10D 84/907
Comprising field effect technology: cMOS gate arrays
H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts

Family

Application63/018,132Us provisional application · filed 30 Apr 2020
Application17/185,464Division · filed 25 Feb 2021
Application18/448,101Continuation · filed 10 Aug 2023
Application19/286,643Continuation
Application18/448,101Division
US 11,923,369 B2Related patent
US 2021/0343744 A1Published application
US 2023/0402461 A1Published application
US 2025/0359326 A1This patent

From the US filing history. Foreign family members aren’t listed.