Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Cheng WU, Li-Feng TENG
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Abstract
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
Claims20
A semiconductor device, comprising:
- a tunnel oxide layer disposed on a substrate;
- a high-k dielectric layer formed on the tunnel oxide layer;
- a floating gate made of a first polysilicon layer and disposed over the high-k dielectric layer;
- a control gate;
- a dielectric layer disposed between the floating gate and the control gate;
- an interfacial silicon oxide layer formed between the tunnel oxide layer and the high-k dielectric layer;
- and
- a select gate formed over the interfacial silicon oxide layer and separated from the floating gate by a sidewall spacer,
- wherein the high-k dielectric layer does not extend below the select gate.
A semiconductor device, comprising:
- a substrate comprising a step formed between a memory cell area and a logic circuit area;
- a non-volatile memory formed in the memory cell area;
- and
- a logic circuit including a field effect transistor (FET) formed in the logic circuit area,
- wherein the non-volatile memory comprises:
- a tunnel oxide layer disposed on a substrate;
- a high-k dielectric layer formed on the tunnel oxide layer;
- a floating gate made of a first polysilicon layer and disposed over the high-k dielectric layer;
- a control gate;
- a dielectric layer disposed between the floating gate and the control gate;
- an interfacial silicon oxide layer formed between the tunnel oxide layer and the high-k dielectric layer;
- and
- a select gate formed over the interfacial silicon oxide layer and separated from the floating gate by a sidewall spacer,
- wherein the high-k dielectric layer does not extend below the select gate.
A method of manufacturing a semiconductor device, comprising:
- forming a substrate comprising a step between a memory cell area and a logic circuit area;
- depositing a tunnel oxide layer over the substrate in the memory cell area;
- depositing an interfacial silicon oxide layer over the tunnel oxide layer in the memory cell area and over the substrate in the logic circuit area;
- depositing a high-k dielectric layer on the tunnel oxide layer in the memory cell area and over the substrate in the logic circuit area;
- depositing a first polysilicon layer over the memory cell area and the logic circuit area;
- depositing a dielectric layer over the memory cell area and the logic circuit area;
- patterning the dielectric layer such that the dielectric layer is formed only over the memory cell area;
- patterning the high-k dielectric layer, the first polysilicon layer, and the dielectric layer in the memory cell area to thereby form a floating gate made of the first polysilicon layer and disposed over the high-k dielectric layer;
- and
- forming a select gate over the interfacial silicon oxide layer in the memory cell area adjacent to the floating gate, such that the high-k dielectric layer does not extend below the select gate.
Dependencies are inferred from the claim text.