High performance embedded 1t1c memory cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChieh Lee, Chi Lo, Yi-Ching LIU, Yih Wang
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Abstract
A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.
Claims20
A memory device, comprising:
- a plurality of memory cells formed along a back surface of a substrate, each memory cell comprising:
- a transistor;
- a word line disposed above the transistor and operatively coupled to the transistor;
- a bit line disposed below the transistor and operatively coupled to the transistor
- a first capacitor disposed above the transistor and operatively coupled to the transistor in series;
- and
- a second capacitor disposed above the first capacitor and operatively coupled to the first capacitor in series,
- wherein the transistor, the first capacitor, and the second capacitor extend long a vertical direction, the word line extends along a first horizontal direction perpendicular to the vertical direction, and the bit line extends along a second horizontal direction perpendicular to the vertical direction and the first horizontal direction.
A memory device, comprising:
- a memory cell formed along a back surface of a substrate, the memory cell comprising:
- a transistor;
- a word line disposed above the transistor and operatively coupled to the transistor;
- a bit line disposed below the transistor and operatively coupled to the transistor
- a first capacitor disposed above the transistor and operatively coupled to the transistor;
- and
- a second capacitor disposed above the first capacitor and operatively coupled to
- the first capacitor,
- wherein the transistor, the first capacitor, and the second capacitor extend long a vertical direction, the word line extends along a first horizontal direction perpendicular to the vertical direction, and the bit line extends along a second horizontal direction perpendicular to the vertical direction and the first horizontal direction.
A memory device, comprising:
- plurality of a memory cells formed along a back surface of a substrate, each memory cell comprising:
- a transistor including a source contact, a drain contact, and a gate electrode;
- a word line disposed above the transistor and operatively coupled to the gate electrode of the transistor;
- a bit line disposed below the transistor and operatively coupled to the drain contact of the transistor;
- a first capacitor disposed above the transistor and operatively coupled to the source contact of the transistor;
- and
- a second capacitor disposed above the first capacitor and operatively coupled to the first capacitor.
Dependencies are inferred from the claim text.