Successive approximation register analog-to-digital converter and operating method thereof

An operating method of an analog-to-digital converter, the analog-to-digital converter comprising a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator, a most significant bit (MSB) of the first capacitor array and the second capacitor array respectively including two capacitors and a (MSB-1) of the first capacitor array and the second capacitor array respectively including one capacitor, the operating method comprising:

• coupling the two capacitors of the MSB and the one capacitor of the (MSB-1) of the first and second capacitor arrays to a common voltage;
• grounding the two capacitors of the MSB of the first capacitor array upon a first analog input inputted into the non-inverting input terminal being larger than a second analog input inputted into the inverting input terminal;
• and
• coupling the two capacitors of the MSB of the first capacitor array to a reference voltage upon the first analog input being smaller than the second analog input, wherein
• the reference voltage is 2 times of the common voltage.

An operating method of an analog-to-digital converter, the analog-to-digital converter comprising a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator, a most significant bit (MSB) of the first capacitor array and the second capacitor array respectively including four capacitors, a (MSB-1) of the first capacitor array and the second capacitor array respectively including two capacitors and a (MSB-2) of the first capacitor array and the second capacitor array respectively including one capacitor, the operating method comprising:

• coupling the four capacitors of the MSB, the two capacitors of the (MSB-1) and the one capacitor of the (MSB-1) of the first and second capacitor arrays to a common voltage;
• grounding the four capacitors of the MSB of the first capacitor array upon a first analog input inputted into the non-inverting input terminal being larger than a second analog input inputted into the inverting input terminal;
• and
• coupling the four capacitors of the MSB of the first capacitor array to a reference voltage upon the first analog input being smaller than the second analog input, wherein
• the reference voltage is 2 times of the common voltage.