Physically unclonable function device

A physically unclonable function (PUF) device, comprising:

• first through fifth inverters connected in series, each of the first through fifth inverters including an input and an output;
• first through fourth common outputs;
• and
• first through eighth resistive memory devices (RMDs), wherein:
• the first and second RMDs have a first common connection,
• the first RMD is connected between the first common connection and the first inverter output, and
• the second RMD is connected between the first common connection and the second inverter output;
• a third RMD and a fourth RMD, wherein:
• the third and fourth RMDs have a second common connection,
• the third RMD is connected between the second common connection and the second inverter output, and
• the fourth RMD is connected between the second common connection and the third inverter output;
• a fifth RMD and a sixth RMD, wherein:
• the fifth and sixth RMDs have a third common connection,
• the fifth RMD is connected between the third common connection and the third inverter output, and
• the sixth RMD is connected between the third common connection and the fourth inverter output;
• and
• a seventh RMD and an eighth RMD, wherein:
• the seventh and eighth RMDs have a fourth common connection,
• the seventh RMD is connected between the fourth common connection and the fourth inverter output, and
• the eighth RMD is connected between the fourth common connection and the fifth inverter output,
• wherein the first inverter is configured to receive a programming voltage and the first through fourth common outputs are configured to float in a randomized programming operation.

A physically unclonable function (PUF) device, comprising:

• a first inverter including a first inverter gate connection and a first inverter drain connection;
• a second inverter including a second inverter gate connection and a second inverter drain connection,
• wherein the first inverter drain connection is electrically connected to the second inverter gate connection,
• a common output connection;
• a first unipolar memristor electrically connected to the first inverter drain connection and the common output connection;
• and
• a second unipolar memristor electrically connected to the second inverter drain connection and the common output connection,
• wherein,
• in a randomized programming operation, the PUF device is configured to apply a voltage to the first inverter gate connection and float the common output connection.